Various hardware mechanisms exist in multi-processor and/or multi-core systems to enable individual cores to send messages between the individual cores. For example, the Intel IXP2xxx series of network processors has multiple hardware mechanisms for sending 32-bit messages from one core to another. Also, many microprocessor cores have speculative prefetching hardware that fetches data from one level of the memory hierarchy to one or more levels higher. For example, if a processor detects that the software running on it is repeatedly accessing data with a constant stride, the processor may speculatively fetch the data the processor expects the software will request next.
Often, a message passed between cores will contain an address reference, or pointer. In existing systems, a receiving core's execution pipeline dereferences the pointer and fetches the data from the memory location, as needed. Significant delays may occur waiting for the data to be retrieved before the instruction in the execution pipeline can be performed. One implementation for message passing is described in “IXP2400/2800 Programming: The Complete Microengine Coding Guide,” by Erik J. Johnson and Aaron R. Kunze (INTEL PRESS 2003). Chapter 10 describes message passing.